With the development of semiconductor manufacturing technology, critical dimension (CD) of semiconductor devices is continuously shrinking. In order to solve the problems of power consumption and response time of small-sized devices, techniques such as gate-last and embedded source/drain device have been widely used.
FIG. 1 is a cross-sectional structural diagram of an embedded source/drain MOS transistor in the prior art, comprising: a semiconductor substrate 10; a shallow trench isolation (STI) structure 11 formed in the semiconductor substrate 10; a gate structure 12 formed on the semiconductor substrate 10, wherein the gate structure 12 comprises a gate dielectric layer 12a on the semiconductor substrate 10, a gate electrode 12b on the gate dielectric layer 12a and a spacer 12c enclosing the sidewalls of the gate dielectric layer 12a and the gate electrode 12b; and a source region 13 and a drain region 14 at respective sides of the gate structure 12, wherein the lattice constants of the source region 13 and the drain region 14 are larger than or less than the lattice constant of the semiconductor substrate 10.
A method for forming the source region 13 and the drain region 14 mainly comprises: when the gate structure 12 has been formed, etching the semiconductor substrate 10 at both sides of the gate structure 12 to form an opening, then filling the opening to form the source region 13 and the drain region 14, by epitaxial growth. Generally, the material of the semiconductor substrate 10 is monocrystalline silicon, and for PMOS transistors, the material filled to form the source region 13 and the drain region 14 may be germanium-silicon (SiGe), which has a lattice constant larger than the lattice constant of monocrystalline silicon, and can produce compressive stress in the channel between the source region 13 and the drain region 14, and improve hole mobility; and for NMOS transistors, the material filled to form the source region 13 and the drain region 14 may be silicon carbide (SiC), which has a lattice constant less than the lattice constant of monocrystalline silicon, and can produce tensile stress in the channel between the source region 13 and the drain region 14, and improve electron mobility.
Moreover, in order to further reduce the source/drain contact capacitance and improve device performance, the source region 13 and the drain region 14 are normally formed with their surfaces higher than the surface of the semiconductor substrate, resulting in a raised source/drain structure. However, in any of the structures above, as the size of the device continues to shrink, leakage current Ileak from the source region 13 and the drain region 14 to the semiconductor substrate 10 becomes considerably larger, and performance of the device is significantly degraded.